ALTSHIFT_TAPS and timing issue

I am having some problems going from simulation to synthesis in my design. The simulation works fine while the synthesized and fitted design does not.

I have written a test bench to synthesize a triangle wave on an audio converter. This works fine.

I have written a decimating filter in Verilog that lowers the sample rate by a factor of 8. The decimating filter has 96 taps and I have 18 bit coefficients and 24 bit data feeding into multipliers.

The coefficients are constant and the 24 bit data feeds in from an ALTSHIFT_TAPS IP block.

As 96 taps sucks up a lot of multipliers, I have a 32 value multiplier.

When the data loads I calculate the first 32 taps, on the next clock I calculate taps 33 to 64 and on the next tap I calculate taps 65-96 (then I shift ALTSHIFT_TAPS three times to set up the data for the next load, while shifting in the current data).

I have created a monitor to detect the rising and falling edges of the ramp and this works well in simulation, on the output of the decimator, however the synthesized and fitted design shows a lot of glitches in signal tap.

The timing analysis shows some horrendous timing issues between the 98.304MHz clock that is generated by a PLL, and some of the decimator registers.

Is there anyway of improving this?

I am using Cyclone IV GX and Quartus 14.0.

Are there any design examples for DSP and ALTSHIFT_TAPS?