altpll in zero delay buffer mode with negativ slack

Hi,

in my design i am generating a 150MHz clock through a pll. I want to use this clock for my gate level/vital testbench too.

I configured the altpll megafunction in zero delay buffer mode with two clock outputs. clockout 0 is connected to an output pin (it's a dedicated pll clkout pin). The pll will be compensated for this pin. clockout 1 is connected to the ip in the fpga. I also connected an unused bidir pin to fbmimicbidir.

After synthesis i get crtitical warnings about the "timing not met". The timequest timing analyzer reports ~167MHz for the slow model which is ok since i want to run the design at 150MHz. But the setup, hold and recovery summary gives negative slack values.

My sdc file looks like this:

# #

create_clock -period 20 -name "clk_in" [get_ports OSC_BA]

derive_pll_clocks

derive_clock_uncertainty

set_input_delay -clock clk_in 0 [all_inputs]

set_output_delay -clock clk_in 0 [all_outputs]# #

My problem is that i do not understand why i have this slack problems. When i configure the pll to run in normal mode with no output pin connected to clkout everything seems to be good and i do not get any critical warnings.

Any help is appreciated :)

Jan