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Honored Contributoraltpll in zero delay buffer mode with negativ slack
Hi,
in my design i am generating a 150MHz clock through a pll. I want to use this clock for my gate level/vital testbench too. I configured the altpll megafunction in zero delay buffer mode with two clock outputs. clockout 0 is connected to an output pin (it's a dedicated pll clkout pin). The pll will be compensated for this pin. clockout 1 is connected to the ip in the fpga. I also connected an unused bidir pin to fbmimicbidir. After synthesis i get crtitical warnings about the "timing not met". The timequest timing analyzer reports ~167MHz for the slow model which is ok since i want to run the design at 150MHz. But the setup, hold and recovery summary gives negative slack values. My sdc file looks like this: # # create_clock -period 20 -name "clk_in" [get_ports OSC_BA] derive_pll_clocks derive_clock_uncertainty set_input_delay -clock clk_in 0 [all_inputs] set_output_delay -clock clk_in 0 [all_outputs]# # My problem is that i do not understand why i have this slack problems. When i configure the pll to run in normal mode with no output pin connected to clkout everything seems to be good and i do not get any critical warnings. Any help is appreciated :) Jan3 Replies
Altera_ForumI could resolve all failing paths but one. The path from the clkout 0 to the ext clock pin still reports a slight negative slack. For the moment I am stuck here. The critical paths in my design I had before were gone after some tweaks, basically I inserted additional registers for some input parameters.
But what can I do with the path to the external clock pin? Except for the output buffer inserted during sythesis there is no additional logic between the pll and the output pin. Timequest gives me the following waveform for the failing path: http://user.cs.tu-berlin.de/%7Ejadero/pictures/waveform.png http://i.imagehost.org/view/0166/DE3_Path_1Hold_slack_is0_162_VIOLATED_Waveform- Altera_Forum
@jakobjones:
thanks for your answer. i will have a look at the failing paths. why is it that the pll in zero buffer mode does not meet the timing requirements? in normal mode everything seems to be fine. - Altera_Forum
You need to start by looking at the list of failing paths. What is failing? Then we can look at why.
Jake
