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Honored Contributoraltpll in zero delay buffer mode with negativ slack
Hi, in my design i am generating a 150MHz clock through a pll. I want to use this clock for my gate level/vital testbench too. I configured the altpll megafunction in zero delay buffer mod...
Altera_ForumHonored Contributor
Honored ContributorYou need to start by looking at the list of failing paths. What is failing? Then we can look at why.
Jake
