altpll in zero delay buffer mode with negativ slack

I could resolve all failing paths but one. The path from the clkout 0 to the ext clock pin still reports a slight negative slack. For the moment I am stuck here. The critical paths in my design I had before were gone after some tweaks, basically I inserted additional registers for some input parameters.

But what can I do with the path to the external clock pin? Except for the output buffer inserted during sythesis there is no additional logic between the pll and the output pin.

Timequest gives me the following waveform for the failing path:

http://user.cs.tu-berlin.de/%7Ejadero/pictures/waveform.png

http://i.imagehost.org/view/0166/DE3_Path_1Hold_slack_is0_162_VIOLATED_Waveform