Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributoraltpll in zero delay buffer mode with negativ slack
Hi, in my design i am generating a 150MHz clock through a pll. I want to use this clock for my gate level/vital testbench too. I configured the altpll megafunction in zero delay buffer mod...
Altera_ForumHonored Contributor
Honored Contributor@jakobjones:
thanks for your answer. i will have a look at the failing paths. why is it that the pll in zero buffer mode does not meet the timing requirements? in normal mode everything seems to be fine.
