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Altera_Forum
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16 years ago

altpll in zero delay buffer mode with negativ slack

Hi, in my design i am generating a 150MHz clock through a pll. I want to use this clock for my gate level/vital testbench too. I configured the altpll megafunction in zero delay buffer mod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

@jakobjones:

thanks for your answer. i will have a look at the failing paths.

why is it that the pll in zero buffer mode does not meet the timing requirements? in normal mode everything seems to be fine.