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Altera_Forum
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15 years ago

ALTMEMPHY Debug GUI: Fails Read Resynch Phase Cal Rst

I'm debugging a DDR2 SO-DIMM design that doesn't work (the example top design seemingly doesn't do anything). I enabled the debug interface per the EMI handbook (debug section) and ran the Debug GUI....
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Does the example project generated by the IP work?

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No, this is the project i'm running. The project generated by the IP must however be modified to run in a real FPGA. I have essentially created a new top-level block that connects to the clock pin and DDR2 SO-DIMM pins. Inside, the test HPCII DDRs 'driver' and controller are used as-is.