ALTLVDS_RX->LVDS serdes Link Training

Thanks for response, i will look into that. As i mentioned, i am using 8 instance of ALTLVDS_RX for data channel. Reason behind that is rearrangement of frame will not much complicated. Can we use "rx_channel_data_align" for realignment? In training phase, when we not find training pattern then we assert "rx_channel_data_align" for one clock and then de-assert it.This can be done till training pattern will be not found. this can be done for all 8 data channel. Same for synchronous channel to get sync code (training pattern, Frame start, Frame end...etc). DPA tab is not enabled/ don't allow to do any changes.

Please let me know this way i can proceed?

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Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for link training.

I have used "ALTLVDS_RX" component for each LVDS data channel and sync channel (9's ALTLVDS_RX). I have query that how to do the link training?

In ALTLVDS_RX i have observed that we have "rx_data_align" which will be input port after making tick while generating component. So, from where this input is controlled or generate. What mechanism or logic is required for this, if it will resolve our bit align/ bit slip for link training. Else what we need to do for this....:confused::confused::confused:

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Why build 9 separate instances? You can build one ALTLVDS_RX instance with up to 64 channels. Much easier to work with one module, especially when it comes to alignment. And if you're in a family that supports DPA I highly recommend using it. DPA takes care of the bit alignment for you and it then tracks alignment continuously during run-time. If you don't use DPA then you have to do bit alignment yourself. I've done it - it's not that complicated. But then the alignment is static. Checking alignment manually during run-time is normally difficult to do because you have to switch back into training mode. DPA is definitely the way to go if you have the option.

I'm not sure I answered your questions but if not then let me know and I'll take another crack at it.

Thanks Rsysc.... Cyclone V:5CGTFD7D5F27C7 device is targeted for Data rate of 576 Mbps. Not using DPA (DPA setting of ALTLVDS_RX). Rx interface is for CMOS Sensor (for example ON Semi).

As i told in my previous query that for each channel i used "ALTLVDS_RX" . So, if TX is transmitting 128 bit through 8 data channel, shall i assume all 8 ALTLVDS_RX [1:8 (channel : deseialization factor)], each will get 8 bit of 128 bit and those received data will be align & there will be no bit slip?

What device and interface speed? Are you doing Dynamic-Phase Alignment(DPA)?

Most LVDS interfaces "close timing", i.e. the parallel bus is all captured correctly and synchronously. Only at the really high speeds with DPA on might each lane align indpendently, in which case you need to align the lanes.

Assuming you are closing timing, the sync is generally used to do word alignment, i.e. the data coming out is supposed to be D7_D6...D0, but might be something like D2_D1_D0_D7_D6...D3(where the D2-D0 is an adjacent word to D7-D3). If the sync is supposed to output a specific pattern, then just shift all the channels until sync has that patter, and the data channels will also be word aligned.