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Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for link training.
I have used "ALTLVDS_RX" component for each LVDS data channel and sync channel (9's ALTLVDS_RX). I have query that how to do the link training?
In ALTLVDS_RX i have observed that we have "rx_data_align" which will be input port after making tick while generating component. So, from where this input is controlled or generate. What mechanism or logic is required for this, if it will resolve our bit align/ bit slip for link training. Else what we need to do for this....:confused::confused::confused:
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Why build 9 separate instances? You can build one ALTLVDS_RX instance with up to 64 channels. Much easier to work with one module, especially when it comes to alignment. And if you're in a family that supports DPA I highly recommend using it. DPA takes care of the bit alignment for you and it then tracks alignment continuously during run-time. If you don't use DPA then you have to do bit alignment yourself. I've done it - it's not that complicated. But then the alignment is static. Checking alignment manually during run-time is normally difficult to do because you have to switch back into training mode. DPA is definitely the way to go if you have the option.
I'm not sure I answered your questions but if not then let me know and I'll take another crack at it.
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