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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks Rsysc.... Cyclone V:5CGTFD7D5F27C7 device is targeted for Data rate of 576 Mbps. Not using DPA (DPA setting of ALTLVDS_RX). Rx interface is for CMOS Sensor (for example ON Semi).

As i told in my previous query that for each channel i used "ALTLVDS_RX" . So, if TX is transmitting 128 bit through 8 data channel, shall i assume all 8 ALTLVDS_RX [1:8 (channel : deseialization factor)], each will get 8 bit of 128 bit and those received data will be align & there will be no bit slip?