Forum Discussion
Honored ContributorALTLVDS_RX->LVDS serdes Link Training
Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for link training.
I have used "ALTLVDS_RX" component for each LVDS data channel and sync channel (9's ALTLVDS_RX). I have query that how to do the link training? In ALTLVDS_RX i have observed that we have "rx_data_align" which will be input port after making tick while generating component. So, from where this input is controlled or generate. What mechanism or logic is required for this, if it will resolve our bit align/ bit slip for link training. Else what we need to do for this....:confused::confused::confused:25 Replies
Altera_ForumHi josy&Rysc,
Thanks a lot. I'll try each possibility after i receive the board. Best Regard- Altera_Forum
In fact, that is what you want to do. Since each channel calibrates independently, it's possible for them to be off from each other. I'll admit, this is a strange thing, as I recommend doing this alignment, but I know of users who have put down DPA designs, never calibrate, and have it work. I think they are at speeds and have layouts where the DPA always aligns to the center of the same bit. Note that the DPA chooses a sampling clock for the most margin. Let's say in one channel it thinks everything is fine, but the channel next to it there are some slightly different delays, and it decided to choose a sampling clock one cycle over, in which case the bits are not aligned between channels. Sending a known patter(which most ADCs do, as far as I know) can allow you to calibrate, and would also alleviate the need for FCO.
- Altera_Forum--- Quote Start --- Hi Rysc, Yes, DCO is the source sycnrous clock, together with the output LVDS data. The FCO is the fram clock output, which will indicate the data word edge. Normally, FCO would be process like LVDS output data channel. That's why i said it will consume fpga lvds_rx channels. --- Quote End --- If the ADC used has a loadable testpattern you could do without the FCO signals and do a bitslip alignment on each ADC channel.
- Altera_Forum--- Quote Start --- All three ADC chips must be driven by the same source clock, so the DCO of the one you use has a 0PPM difference from the other chips. From your description, there is no difference between the three ADCs, so there's no reason I could say one is better, but no, I assume they're laid out similar and it wouldn't matter. I assume DCO is the clock, what's the FCO? I'm not sure without knowing it's functionality. --- Quote End --- Hi Rysc, Yes, DCO is the source sycnrous clock, together with the output LVDS data. The FCO is the fram clock output, which will indicate the data word edge. Normally, FCO would be process like LVDS output data channel. That's why i said it will consume fpga lvds_rx channels.
- Altera_Forum
All three ADC chips must be driven by the same source clock, so the DCO of the one you use has a 0PPM difference from the other chips. From your description, there is no difference between the three ADCs, so there's no reason I could say one is better, but no, I assume they're laid out similar and it wouldn't matter.
I assume DCO is the clock, what's the FCO? I'm not sure without knowing it's functionality. - Altera_Forum--- Quote Start --- With DPA, each channel is dynamically captured, so no matter what your trace length is, you will get clean data. The problem is that the data from adjacent channels is not necessarily aligned, so the closer your trace lengths the less difference there will be when entering the fabric. --- Quote End --- Hi Rysc, Thanks for you reply quickly. 1. For i want to combine 3 ADC chips output into one alt-lvds receiver module, i have chose one of these 3 ADC chips DCO to feed into fpga. Do you think which one selected is better, or anyone is ok? 2. In order to save LVDS RX pins, can i only connect one of three FCO into fpga? Even i have enough lvds-rx pins to reciever all three fco, i just want to know if i can combine more than 3 ADC chips into one alt-lvds reciever module. Best Regard
- Altera_Forum
With DPA, each channel is dynamically captured, so no matter what your trace length is, you will get clean data. The problem is that the data from adjacent channels is not necessarily aligned, so the closer your trace lengths the less difference there will be when entering the fabric.
- Altera_Forum--- Quote Start --- That is another big benefit of DPA. Since each channel aligns itself, you can use a single PLL for all three interfaces. --- Quote End --- Hi Rysc, Thanks for you reply. Do I need to match the trace lines' length equeal among the 3 ADC output LVDS signals outside the fpga? Or just make the ADCs sampling clock traces equal lengh? Best Regard
- Altera_Forum
That is another big benefit of DPA. Since each channel aligns itself, you can use a single PLL for all three interfaces.
- Altera_Forum--- Quote Start --- Why build 9 separate instances? You can build one ALTLVDS_RX instance with up to 64 channels. Much easier to work with one module, especially when it comes to alignment. And if you're in a family that supports DPA I highly recommend using it. DPA takes care of the bit alignment for you and it then tracks alignment continuously during run-time. If you don't use DPA then you have to do bit alignment yourself. I've done it - it's not that complicated. But then the alignment is static. Checking alignment manually during run-time is normally difficult to do because you have to switch back into training mode. DPA is definitely the way to go if you have the option. I'm not sure I answered your questions but if not then let me know and I'll take another crack at it. --- Quote End --- Hi rsefton, I want to process three ADC devices, which output LVDS data lines. Can i conbine these 3 ADC outputs into one ALTVLDS_RX module? My devcie can enable DPA. Regards
