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Mikexx
Occasional Contributor
Occasional ContributorALTIOBUF - Enable input buffer dyamic delay chain
I get a series of errors when this feature is ticked in the ALTIOBUF: Cyclone V Quartus 20.1 Error (129036): Output port DATAOUT on atom "DQS_Diff_4:u_DQS_Diff_4|DQS_Diff_4_iobuf_bidir_3qg1:DQS_Di...
MikexxOccasional Contributor
Occasional ContributorMany thanks for looking into this.
The intent was to delay the DQS inputs by a small amount and to use this internally within the FPGA rather than feeding a DDR IO primitive.
Although the projects were a cut-down of the original project, the intent was to drive the DDR clock in signal with DQS_in to convert the DDR data into SR data.
The datasheets for LPDDR memory suggest that it is the DQS signals that should be delayed to match the DQ data valid time, hence my approach.
