Forum Discussion
EthanLi
Occasional Contributor
2 years agoHi,
This is Ethan from Intel AE team.
I have checked your design and find that the data_out(DQS_in) from the input delay chain connected directly to the output pin in the top design. Once you use the delay chain you should not connect the data_out of the delay chain to the output port of the top level directly, you may connect the data_out to the input of fifo or ddio etc.
I will upload the design compiled successfully.
Thanks,
Ethan