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Honored Contributor
Honored ContributorALTGX rx_clkout -> ALTPLL
I am using quartus/9.1. In my design, the ALTGX rx_clkout is running at 250 MHz with a receive data width of 32 bits. The outputs ALTGX are then “stepped down” to run at 125 MHz with a 64 bit ...
Altera_ForumHonored Contributor
Honored ContributorHow do you clock the FPGA fabric ?
Do you have any external reference or system clock feeding a dedicated clock input or do you expect to use the GXB recovered clock only !?
