Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ALTGX rx_clkout -> ALTPLL

I am using quartus/9.1.

In my design, the ALTGX rx_clkout is running at 250 MHz with a receive data width of 32 bits. The outputs ALTGX are then “stepped down” to run at 125 MHz with a 64 bit datapath, and the majority of my logic runs at 125 MHz. As such, I need to take the rx_clkout and divide it by two for use to generate a synchronous 125 MHz clock. I started to do this division using an ALTPLL.

However, I discovered that the clock inputs to the ALTPLL can only come from another PLL or a dedicated PLL clock pin. Quartus delivers this error message:

Error: Clock input port inclk[0] of PLL "..." must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

How would you suggest dividing the ALTGX clock by two if an ALTPLL cannot be used?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    How do you clock the FPGA fabric ?

    Do you have any external reference or system clock feeding a dedicated clock input or do you expect to use the GXB recovered clock only !?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It's worth noting that the reason they don't let you use the recovered receive clock or a PLL output as the reference clock for the transmit PLL is because of jitter. Just keep that in mind as you consider these options:

    1 - Do you just need a 125MHz clock or does it need to be locked to the receive clock frequency?

    1 - If you have an external clock feedback path (output clock fed back to an input clock pin). You could take the receive clock, divide it down and feed it back to yourself. Then Quartus won't know the difference. However, jitter will likely be an issue.

    2 - Harass your Altera FAE until he gives you the secret method for allowing Quartus to ignore the error and indeed use the PLL output as the transmit PLL reference clock. This of course assumes that there is such a secret method and again, jitter may be an issue.

    3 - The conventional approach is to have some external clock generator that you can lock to the receive clock frequency. This requires a phase-frequency detector and of course the ability to adjust or pull the external clock. The technique is known as reclocking. In the video world we call it genlock.

    Jake