ALTGX rx_clkout -> ALTPLL

It's worth noting that the reason they don't let you use the recovered receive clock or a PLL output as the reference clock for the transmit PLL is because of jitter. Just keep that in mind as you consider these options:

1 - Do you just need a 125MHz clock or does it need to be locked to the receive clock frequency?

1 - If you have an external clock feedback path (output clock fed back to an input clock pin). You could take the receive clock, divide it down and feed it back to yourself. Then Quartus won't know the difference. However, jitter will likely be an issue.

2 - Harass your Altera FAE until he gives you the secret method for allowing Quartus to ignore the error and indeed use the PLL output as the transmit PLL reference clock. This of course assumes that there is such a secret method and again, jitter may be an issue.

3 - The conventional approach is to have some external clock generator that you can lock to the receive clock frequency. This requires a phase-frequency detector and of course the ability to adjust or pull the external clock. The technique is known as reclocking. In the video world we call it genlock.

Jake