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Sorry I am not fully understand this. The timestamps come in a combination of Alphabets and Numbers. I thought ASCII has the least bits to represent them. How do they occupies less BW if using binary form? for example, "A" and "3" are decimal 63 and 51 in ASCII table. They are in text form when being sent to FPGA. Then what should I print in the storage device to save bandwidth?
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Time stamps do not have to be ASCII. You can store an accurate timestamp using a single 32-bit integer, and an even more accurate timestamp using a 64-bit integer.
For example, in some of my designs I have version and timestamp generics that get passed down to read-only status registers. Software can then report the hardware version, and its build timestamp.
Using the Cygwin/Linux date command you can get:
# Build timestamp
set timestamp
or in pure Tcl
# Build timestamp# - Tcl returns the same as
set timestamp
Read the Linux man pages or the Tcl pages for the formatting, and commands to convert the 32-bit value back into a timestamp string.
Your binary data format should have a definition document. The format might be something like:
1) Endian flag
2) 32-bit timestamp
3) Sampling frequency
4) Sample bit width
5) Number of samples
6) Sample data
If you do not put an endian flag in the data format, then you must define the binary data format as big-endian-only or little-endian-only. So that different machine architectures will know how to read the binary files.
I use CORBA Common Data Representation (CDR) for my binary data formats. The ACE C++ library has stream encode and decode functions. The binary data format is used for passing data between clients and servers, and for writing binary data files.
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Oh, now I get it. However, I do not use a filter. I am sampling the raw analog into FPGA to analyse the voltage level of sampled pulses, regardless to what the source is streaming. I should say it at the beginning that my system is not Audio/Video system. It is a monitoring system which will sample whatever kind of random noise/transients waveforms or pulses from a constant low frequency line. This is the reason I will shift to higher ADC frequency incrementally after the first design.
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You need to check what the signal looks like with a wide bandwidth oscilloscope or spectrum analyzer. Your ADC may have a wider input bandwidth than your sampling rate, and if it does, then signal will alias into the digital baseband produced by the ADC. This may corrupt your results.
If you are only interested in signals up to 200MHz (for a 400MHz clock rate), then you should really have a 200MHz low-pass filter.
Cheers,
Dave
Honored Contributor
