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If you store a 32-bit hex value as the 8 ASCII characters "12345678", it uses more bits than storing the binary data directly. Each ASCII character requires 8-bits to represent, whereas the character represents only 4-bits of the number you are storing.
The binary file will be half the size of an ASCII file.
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Sorry I am not fully understand this. The timestamps come in a combination of Alphabets and Numbers. I thought ASCII has the least bits to represent them. How do they occupies less BW if using binary form? for example, "A" and "3" are decimal 63 and 51 in ASCII table. They are in text form when being sent to FPGA. Then what should I print in the storage device to save bandwidth?
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I understand, but my question was what is the exact bandwidth you are sampling.
If you are sampling a signal at 400MHz, you will have to filter it first with analog filters. Its unlikely you can get extremely sharp analog filters, so you will sample some bandwidth that is aliased, or has low signal. This part of the bandwidth can be digitally filtered, and the signal can then be re-sampled to a lower data rate. The re-sampled data can then be stored. This will save you bandwidth.
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Oh, now I get it. However, I do not use a filter. I am sampling the raw analog into FPGA to analyse the voltage level of sampled pulses, regardless to what the source is streaming. I should say it at the beginning that my system is not Audio/Video system. It is a monitoring system which will sample whatever kind of random noise/transients waveforms or pulses from a constant low frequency line. This is the reason I will shift to higher ADC frequency incrementally after the first design.
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Altera provides simulation versions of their IP. If you can get Modelsim working for your design, then you need to synthesize and check that the device has enough logic and can meet timing. I'd recommend incrementally testing (simulate plus synthesize) each interface, and obtain a logic estimate at each stage. Then as you start to integrate the system, you will have an expectation of logic usage. If each subsystem meets timing, then the whole system should meet timing too.
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This is exactly what I have in mind but unsure. With your words, now it is confirmed. hooray~
Rgds,
Wai Siang
Honored Contributor
