Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- origianlly the timestamp is in ASCII. How do we save in binary bits that occupies less bandwidth? --- Quote End --- If you store a 32-bit hex value as the 8 ASCII characters "12345678", it uses more bits than storing the binary data directly. Each ASCII character requires 8-bits to represent, whereas the character represents only 4-bits of the number you are storing. The binary file will be half the size of an ASCII file. --- Quote Start --- There are 3 operating mode in my design plan. The ADC input is 400MSa/s. The FPGA route the sample to the DDR3 in realtime. Then write to SATA HDD in max speed that the HDD supports (apparently it is at data rate of SATA2/3). User may request remote download through wireless link, then FPGA will read from SATA and send over the wireless module (wireless eva kit is usually at USB rate). --- Quote End --- I understand, but my question was what is the exact bandwidth you are sampling. If you are sampling a signal at 400MHz, you will have to filter it first with analog filters. Its unlikely you can get extremely sharp analog filters, so you will sample some bandwidth that is aliased, or has low signal. This part of the bandwidth can be digitally filtered, and the signal can then be re-sampled to a lower data rate. The re-sampled data can then be stored. This will save you bandwidth. --- Quote Start --- The system has different features integrated altogether in an FPGA. It may not synthesizable even it is working in ModelSim. Isnt Quartus 2 only works with hardware? --- Quote End --- Altera provides simulation versions of their IP. If you can get Modelsim working for your design, then you need to synthesize and check that the device has enough logic and can meet timing. I'd recommend incrementally testing (simulate plus synthesize) each interface, and obtain a logic estimate at each stage. Then as you start to integrate the system, you will have an expectation of logic usage. If each subsystem meets timing, then the whole system should meet timing too. Cheers, Dave