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user153746's avatar
user153746
Icon for New Contributor rankNew Contributor
3 years ago

Altera Stratix V FPGA (P/N: 5SGSMD8N2F45C2L)

This part is supplied via two separate power rails (1.8V and 3.3V). The 1.8V rail supplies the VCCINT and VCCI02 pins, and the 3.3V supplies the the VCCI01 pins. The 1.8V rail comes up to voltage in ...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


The power-on reset (POR) circuitry keeps the FPGA in the reset state until the power supply outputs are in the recommended operating range.


A POR event occurs from when you power up the FPGA until the power supplies reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the device I/O pins and programming registers remain tri-stated, during which device configuration could fail.


The tRAMP for Stratix V is between 200 microseconds to 100 ms for Standard POR while 200 microseconds to 4 ms for Fast POR.