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Honored ContributorALT_PLL SIMULATION with Cyclone V, cannot get activity on outputs in Modlesim
Hello, I am using Quartus II version 15 and have started with very simple code that only implements the ALT_PLL function and nothing more. The PLL is very basic, 70MHz in, 3 out... 1 at 70MHz 0degree shift, 2 at 105MHz 90 degree shift,3 at 42MHz 0 degree shift.
Then I created a test bench for the code and have the clock in toggling at 70MHz,the reset starts at 0,then after 100us goes high then after 200us goes low again. but no matter what I do I cannot get any simulated output. Please need help for I really cannot start other pars of design until I asure my clocking will be correct. Thanks.6 Replies
Altera_ForumWhat tool are you simulating it with? Modelsim_ase or something else?
- Altera_Forum
What is the PLL lock signal when the issue occur?
- Altera_Forum
Hi,
Are you able to compile the design in CV at all? I believe when using V series, the pll used was changed from ALT_PLL to Altera PLL. Could this be the problem? - Altera_Forum
ah_zhi02 has brought up a valid point. As I know, ALTPLL instances are supported in IV series ie Stratix IV and older devices. Starting from V series devices ie Cyclone V, we should use Altera PLL to instantiate the PLL.
- Altera_Forum
I don't understand the ALT_PLL point. ALT_PLL instances without device specifc parameters will be simply mapped to Altera PLL. Otherwise expect a warning.
I expect a rather trivial issue. Did you set Modelsim time resolution to 1 ps, as required for PLL simulation? - Altera_Forum
The PLL is working fine in my design simulation. I will put it here for your reference.:)
