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Altera_Forum's avatar
Altera_Forum
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14 years ago

All Purpose sign extension VHDL?

Hi, I was just wondering how it would be possible to make an all purpose sign extension entity in VHDL. So I created this sign extension entity but it will only work if the input is 6 bits long. If...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In addition to the ports, you should add two generics on your entity, and use those to define the sizes of your input and output vectors.

As for your second question, you need to assign individually each signal. Or if your signals are in an array, you can assign each one of them with the same value using the (others => xxx) syntax.