Aligning a derived PLL clock with an external clock

I don't really see where or what the problem is.

I can input 120MHz to PLL and produce 120MHz, 60MHz & 40MHz & 30MHz & 20MHz & 10MHz ...etc all with the PLL phase output for each set to same value(in degrees or picosec). The compiler will tell you how much accuracy it achieved.

In a project of mine I did that with an external clk of 20.48MHz and produced a catalogue of other synchronised clks(204.8, 102.4, 51.2,20.48,10.24) without problem.

I have to trust the PLL unless proved otherwise, just like I trust an AND function will be AND.