Aligning a derived PLL clock with an external clock

I was confused about your question, thinking it's an internal clock. If it's external, then it's just regular I/O timing. All delays in the FPGA are accounted for(PLL delays, compensation, etc.). If the external clock is 120MHz and the internal clock is 60MHz, then you might have a larger window to work with, I don't know. Bottom line is you need to constrain your I/O, just like any other project, and if you meet timing it will work.