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And of course they're is going to be some difference, the questions is if timing analysis handles this. It does, and I have to say, almost every design I get has multiple clocks coming out of PLLs and they safely pass data back and forth as if they were synchronous.
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I would worry less if the two clocks came out of the PLL. The troubling issue is that one of the clocks is external, and I'm not sure the timing analyzer knows how to handle this correctly. I need to know the real phase-misalignment between the input and the PLL output, as even a few nanoseconds are important in this case.
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