Aligning a derived PLL clock with an external clock

Yes and no. There's no real way to tap into the core and see the clocks(I've seen people wanting to measure PLL jitter inside the part, for whatever reasons, and it just wasn't possible, as bringing the clocks out through I/O buffers and what not adds jitter).

Note that in this case you do want the internal routing differences, since they're valid on transfers. It's really just differences in the output buffer you don't want. I would just bring them out to adjacent I/O and see what the difference is.

And of course they're is going to be some difference, the questions is if timing analysis handles this. It does, and I have to say, almost every design I get has multiple clocks coming out of PLLs and they safely pass data back and forth as if they were synchronous.