Forum Discussion
Hi,
Please refer the below link for running the HPS example design on this development kit. This link will help on the board step and .pof & .jic flashing.
Regards
Tiwari
- shivajim2 years ago
New Contributor
Hi,
Thanks for the link, I tried the same. For some reason it didn't allow reflashing after first time flashing the images, but after changing the switch settings I was able to re-program. also I observed that if the uboot merged *.jic's were flushed to the Agilex, then sdm got stuck on the bootloop, u-boot fails to load image from qspi, then falls back and continues after wdt timeout. I also found the same popup when I tried to erase fpash/re-pogram golden *.jic in this situation, changing the switch helped to load golden *.jic.
Thanks,
Shivaji M
- GeorgeAndrawos4 months ago
New Contributor
Same here, I switched temporarily to jtag msel to flash the jic then it worked.
- FvM4 months ago
Super Contributor
Hi,
JTAG configuration, also .jic programming, basically works with all MSEL settings. There might be however a problem if MSEL is set to AS configuration and flash memory holds no valid configuration. FPGA configuration controller may perform endless tries to load the configuration, interfering with two-step .jic programming. Need to disable FPGA configuration controller in programmer options.