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ohfpga1's avatar
ohfpga1
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9 days ago

Agilex5 - Timings configuration

Hi,

in document 813918, I have a question regrading method to define NOR timing, table 115, using Text_delay as conditions for input timings.

this parameter is said dependant  of frequency of interface (note 195), but only one value (max) is given (no min), and this one is greater than half-period and even at clock frequency 166MHz which seems to be considered by datasheet. I don't understand.

Can we get simply Setup and Hold timings for Agilex inputs for AS configuration interface ?

Thanks and regards

 

2 Replies

  • ohfpga1's avatar
    ohfpga1
    Icon for New Contributor rankNew Contributor
    2 hours ago

    Hi Farabi, thanks a lot for your detailed answer.

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    12 hours ago

    Hello, 

     

    To answer your question:

    Table 115 : AS timing parameters is not a setup/hold guarantee table, instead, it is a board-level interface contstraint table, to calculate FPGA + flash + PCB delays. 

     

    Most imporatantly, we need to interpret the skew equation:

    AS_CLK vs AS_DATA : –AS_CLK/2 + Tdo(max) + Tsu < Skew (AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho

    Above equation is not setup/hold spec, but relative arrival window. 

     

    summary above equation: 

    AS_DATA can arrive before or after AS_CLK as long as the skew is bounded.

     

    Reason why Altera dont publish setup/hold time for AS inputs

    a) AS configuration pins are handled by dedicated IOs

    b) Not routed to user IO

    c) exist in different clock domain

     

    While internal margins are:

    a) characterized

    b) guard-band

    c) hidden from user

     

    Altera guarantee the correct operation if you meet the skew rules, instead of publishing internal setup/hold time spec. 

     

    regards,

    Farabi