Agilex5 - Timings configuration

Hello, 

To answer your question:

Table 115 : AS timing parameters is not a setup/hold guarantee table, instead, it is a board-level interface contstraint table, to calculate FPGA + flash + PCB delays. 

Most imporatantly, we need to interpret the skew equation:

AS_CLK vs AS_DATA : –AS_CLK/2 + Tdo(max) + Tsu < Skew (AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho

Above equation is not setup/hold spec, but relative arrival window. 

summary above equation: 

AS_DATA can arrive before or after AS_CLK as long as the skew is bounded.

Reason why Altera dont publish setup/hold time for AS inputs

a) AS configuration pins are handled by dedicated IOs

b) Not routed to user IO

c) exist in different clock domain

While internal margins are:

a) characterized

b) guard-band

c) hidden from user

Altera guarantee the correct operation if you meet the skew rules, instead of publishing internal setup/hold time spec. 

regards,

Farabi