AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

After we updated Quartus from 24.3 to 25.1 version, we are getting this error, if we try to programm design.core.rbf from linux via dt-overlay.

[   15.843462] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: timeout waiting for svc layer buffers

Same design.core.rbf worked with first stage loader from Q24.3. We programmed it from LINUX first with FSBL from Q24.3 succesfully, and then programm QSPI NOR flash with the newly generated design_jic.rpd. After reboot we see that error, if we try to programm design.core.rbf as before.