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MM-ATH's avatar
MM-ATH
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

Hello, I am using HPS-first boot scheme on AGILEX5 AXE5-Eagle dev board. I have suddenly problem with writing FPGA (fpga_core.rbf) from running linux. Before it worked as expected, but now I am gett...
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Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
10 months ago

Hi,


Is this issue still there?

Which Quartus version you are using for old .rbf and new .rbf?

Also, mention the uboot, ATF and kernel versions used?


Regards

Tiwari


MM-ATH's avatar
MM-ATH
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Hi Tiwari,

yes, issue is still there,

Sometimes there is also this error (this design can be programmed also in u-boot):

[    8.577797] fpga_manager fpga0: writing /images/fpga_core.rbf to Stratix10 SOC FPGA Manager
[   11.120096] svc_normal_to_secure_thread: STATUS_ERROR
[   11.125195] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_ERROR
[   11.134790] fpga_manager fpga0: Error after writing image data to FPGA
[   11.141815] fpga_region region0: failed to load FPGA image
[   11.147394] OF: overlay: overlay changeset pre-apply notifier error -14, target: /soc@0/base_fpga_region
[   11.156908] create_overlay: Failed to create overlay (err=-14)

Quartus version is 24.3.1 Build102 01/14/2025 no patches.

Regards

Martin