AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

Hi Tiwari,

yes, issue is still there, Quartus version is 24.3.1 Build102 01/14/2025 (Patches none).

Regards

Martin

Hi Tiwari,

yes, issue is still there,

Sometimes there is also this error (this design can be programmed also in u-boot):

[    8.577797] fpga_manager fpga0: writing /images/fpga_core.rbf to Stratix10 SOC FPGA Manager
[   11.120096] svc_normal_to_secure_thread: STATUS_ERROR
[   11.125195] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_ERROR
[   11.134790] fpga_manager fpga0: Error after writing image data to FPGA
[   11.141815] fpga_region region0: failed to load FPGA image
[   11.147394] OF: overlay: overlay changeset pre-apply notifier error -14, target: /soc@0/base_fpga_region
[   11.156908] create_overlay: Failed to create overlay (err=-14)

Quartus version is 24.3.1 Build102 01/14/2025 no patches.

Regards

Martin

We removed F2HPS bridge from design (we don't need it, it was relict of GHRD design), due debuging of Other problem and since then all designs can be programmed also in linux via dt-overlay (about 7 compilations now).

I am sorry, I forgot to write other versions, so here they are:

kernel is 6.6.37 - 6.6.37-ge98c5f87520c

ATF is 2.11.0 - BL31: v2.11.0(release):QPDS24.3_REL_GSRD_PR

u-boot is U-Boot SPL 2024.04-35103-gdc428c3751