Forum Discussion
emrahener
New Contributor
3 years agoAGILEX Per pin package RLC data
Hi,
I want to generate ibis file for my FPGA design and fooling the procedure described in :
https://community.intel.com/t5/FPGA-Wiki/Generating-an-Agilex-per-pin-RLC-IBIS-ibs-file/ta-p/1342589...
emrahener
New Contributor
3 years agoWhen I try to use the generated ibis file in Cadence Sigrity tool It does not accept the generated ibis file. I used ibischk7 from
https://ibis.org/ibischk7 and the it also could not validate the generated ibis file. I am sending the ibischk7 output ibischeckerr.txt .
The command I am using are in Command.txt
I am attaching all files used in the process.
Kind Regards
Emrah ENER