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emrahener
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3 years ago

AGILEX Per pin package RLC data

Hi, I want to generate ibis file for my FPGA design and fooling the procedure described in : https://community.intel.com/t5/FPGA-Wiki/Generating-an-Agilex-per-pin-RLC-IBIS-ibs-file/ta-p/1342589...
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emrahener
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3 years ago

Hi Aqid,

The RLC file solved the issue with the script. Thanks for your help.

Regards,

Emrah