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emrahener's avatar
emrahener
Icon for New Contributor rankNew Contributor
3 years ago

AGILEX Per pin package RLC data

Hi, I want to generate ibis file for my FPGA design and fooling the procedure described in : https://community.intel.com/t5/FPGA-Wiki/Generating-an-Agilex-per-pin-RLC-IBIS-ibs-file/ta-p/1342589...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thank you for reaching out to Intel FPGA Community.

I have sent the requested file via email. Kindly check your inbox and confirm if you have received it.


Regards,

Aqid