Occasional ContributorAgilex F-Tile bus reversal / twist
Previous (and presumed dead) discussions:
https://community.intel.com/t5/Programmable-Devices/Intel-Agilex-FHT-FGT-lane-swapping/m-p/1453468
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Aglix-F-tile-P-amp-R-error/m-p/1456868
Been trying to drive signals out the QSFP-DD cages on my Agilex 027 SoC evm. Quartus is complaining about the pin assignments when I configure a quad of outputs (one instance, 4 lanes) in Platform Designer. The pins in question, from the SoC evm schematic:
I turned on all 16 FGT transceivers in an F-Tile to see where the compiler wanted to place them. Here's the breakdown of mappings from core signals to I/O pins:
All 16 FGT transceivers assigned. Pins selected by Quartus (no constraints in .qsf) qsfpdd0_tx0 Output PIN_AD7 Quad3[0] qsfpdd0_tx1 Output PIN_AG10 Quad3[1] qsfpdd0_tx2 Output PIN_AH7 Quad3[2] qsfpdd0_tx3 Output PIN_AM7 Quad3[3] hssi4p Output PIN_AC10 Quad2[3] hssi5p Output PIN_Y7 Quad2[2] hssi6p Output PIN_W10 Quad2[1] hssi7p Output PIN_T7 Quad2[0] hssi8p Output PIN_R10 Quad1[3] hssi9p Output PIN_M7 Quad1[2] hssi10p Output PIN_L10 Quad1[1] hssi11p Output PIN_G10 Quad1[0] hssi12p Output PIN_H13 Quad0[3] hssi13p Output PIN_D13 Quad0[2] hssi14p Output PIN_G16 Quad0[1] hssi15p Output PIN_C16 Quad0[0] Note that bits out[3:0] map to Quad3[3:0] but out[7:4] map to Quad2[0:3] - bus twist out[11:8] map to Quad1[0:3] - bus twist out[15:12] map to Quad0[0:3] - bus twist
Appears there's bus twist at the Tile level, then again at the Quad level. So, "bus twist"? Wazzat?
Typically, it's a head-butting of big-endian and little-endian perspectives. Simple verilog example that assigns one 8-bit bus to another:
Abus[7:0] <= Bbus[0:7];
No big deal, right? The values of Bbus got assigned to Abus. What's really happening:
Abus[7] <= Bbus[0]; Abus[6] <= Bbus[1]; Abus[5] <= Bbus[2]; Abus[4] <= Bbus[3]; Abus[3] <= Bbus[4]; Abus[2] <= Bbus[5]; Abus[1] <= Bbus[6]; Abus[0] <= Bbus[7];
I'm running Quartus Pro 23.3, but this was observed in 23.1 and 22.3. If I try to map my output qsfp_dd[0] to pin T7 (which is FGTR13C_TX_Q2_CH0p) I will get an error saying there's no resource available or that the signal must be mapped to a different set of internally-named pins with a [3] suffix. If I twist my bus outputs such that out[3] is mapped to FGT_CH0p, it connects just fine. Notably, I did NOT have this issue with an Agilex AGF014 eval board that I was using previously. That one used E-Tiles, so this might be specific to the F-Tile implementation.
This type of problem is common for bussed signals (vectors) that cross a hierarchy boundary and the top-level and bottom-level declarations have opposite endian-ness.
I'm just going to patch around this issue with a macro-reassignment at my top-level that spackles-over the twist. Would be nice is Altera could fix the source issue in Quartus.
