Agilex E-Tile-Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core

Question

Hello all,I am working on Intel Agilex FPGA(AGFB014R24B2E2V) and Quartus Prime Pro software version 24.1 and AFE79 EVMI generated my JESD204B design example for Agilex 7. The top file requires two clock as input refclk_core and refclk_xcvr. I am getting the below-mentioned error during the fitter stageError(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core. HSSI REFCLK divider "refclk_core~inputFITTER_INSERTED" has core fanouts. Error(16297): An error has occurred while trying to initialize the plan stage. Error: Quartus Prime Fitter was unsuccessful. 2 errors, 2 warnings Error: Peak virtual memory: 3939 megabytes Error: Processing ended: Sat Oct 5 11:49:13 2024 Error: Elapsed time: 00:00:39 Error: System process ID: 6028Kindly help me with this regard.Thank You

harshx · Answer

Hi,Thanks for contacting Intel. I'm assigned to support request.Kindly refer this: Agilex E tile - Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core. - Intel CommunityRegards,Harsh M

amit4 · Answer

Hi Harsh,I have already gone through the mentioned steps..still, I am facing the same error.

harshx · Answer

Hi,Is it possible for you to share your archived design? If yes, kindly attach the file.Regards,Harsh M

amit4 · Answer

Hello, below is the design file

harshx · Answer

Hi,Thank you for sharing the design.I'll update you as soon as I have any findings.Note: It's going to take few more days due to internal some issue.Regards,Harsh M

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Agilex E-Tile-Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core

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