Agilex E-Tile-Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core

Hello all,

I am working on Intel Agilex FPGA(AGFB014R24B2E2V) and Quartus Prime Pro software version 24.1 and AFE79 EVM

I generated my JESD204B design example for Agilex 7. The top file requires two clock as input refclk_core and refclk_xcvr.

I am getting the below-mentioned error during the fitter stage

Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core. HSSI REFCLK divider "refclk_core~inputFITTER_INSERTED" has core fanouts.
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 3939 megabytes
Error: Processing ended: Sat Oct 5 11:49:13 2024
Error: Elapsed time: 00:00:39
Error: System process ID: 6028

Kindly help me with this regard.

Thank You