Forum Discussion

arik's avatar
arik
Icon for New Contributor rankNew Contributor
3 years ago

Agilex E-TILE CPRI PHY

HI I use the Intel Agilex FPGA – AGFB014R24B2E2V. I created the CPRI Phy IP to Line-rate 8 (LR8 (64/66)) and below (LR7 (8/10), LR6 and etc.) – It is not allowed to attache the IP. When I loa...
skbeh's avatar
skbeh
Icon for Contributor rankContributor
3 years ago

CPRI under 10G data rate is using soft-PCS and 8b10b interface which does not support RSFEC.

CPRI above 10G data rate is using hard-PCS and 64b/66b interface with RSFEC.

So it seem there is a limitation to dynamic reconfiguration between 10.1376 Gbps (LR8) 9.8304 Gbps (LR7).


In order to verify whether the method you have used to change the line rate is working, you can try change within the same below 10G data rate, i.e. from 9.8304 Gbps to 6.144 Gbps.