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emrahener's avatar
emrahener
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2 years ago

Agilex DDR4 Interface Debug

EMIF Toolkit does not support Agilex Family FPGAs but EMIF IP user guide still address this toolkit for JTAG debugging. http://www.audentia-gestion.fr/INTEL/PDF/ug-ag-emi.pdf Page :105. Is ther...
emrahener's avatar
emrahener
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2 years ago

Hi,

Can you please be more specific with `EMIF Debug Toolkit has been enabled`. ?

External Memory Interfaces Intel Agilex IP has a parameter in Diagnostics Tab.

Disabled : Certainly we dont want this .

Export : EMIF debug interface IP core is not among available IP list in IP Catalog.

I selected Add EMIF Debug Interface and Rerunned the whole flow starting from Generate HDL. When I downloaded the .sof file I could not see any selection in the system console system (Debugger Tools /System Console).

Since the related parameter is under the title Example Design (Diagnostics Tab not Example Design Tab) I generated the example design and will try downloading the resultant sof file .

Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.