Forum Discussion
Occasional ContributorAgilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy
Hi Steve9 ,
ASIC or ASSP can drive low at power up sequence, but FPGA needs configuration to download the programming file and during configuration time, pin is flowed and pull up on the board. This is nature of the FPGA pins.
But after configuration is done FPGA will assert low during initialization. So it goes like High -> Low -> High
So the FPGA still can drive the pin low or high regardless the termination scheme.
Regards,
Adzim
Occasional ContributorThanks Adzim.
For point 1, the reset_n pin is only connected from Agilex output to SDRAM chip inputs with pullup, so the only thing that can drive the reset_n pin is the Agilex right? And the Agilex can't drive signals until it's powered up. So I'm not sure what you mean by "the power need to apply to reset_n pin". It seems like it would not be possible to meet the datasheet power-up sequence that "Reset_n should be maintained below 0.2 x VDD while supplies ramp up" with the suggested pullup.
For point 2, understood.
Regular ContributorHi Steve9 ,
ASIC or ASSP can drive low at power up sequence, but FPGA needs configuration to download the programming file and during configuration time, pin is flowed and pull up on the board. This is nature of the FPGA pins.
But after configuration is done FPGA will assert low during initialization. So it goes like High -> Low -> High
So the FPGA still can drive the pin low or high regardless the termination scheme.
Regards,
Adzim
