Agilex 5 Transceiver Tx failing for pll lock

Question

Hi,

I am trying to use the Dispaly port IP design example on Agilex 5 device A5ED065BB32AE4SR0 on Arrow AXE5 Eagle development board. However it appears that the Transceiver Tx PLL Lock fails to lock to the clock, while the Rx from the same clock seems to be stable. I have tried this for Banks 4B and 4C using the Display port IP with transceiver toolkit enabled.
I used the autogenerated debug code to measure the gts clocks for rx and tx and although Rx is stable at 8GHz, Tx seems to be struggling around 5GHz range.
I am using PMA direct clock for this. Without Tx PLL locked, I would not be able to test Near side Loopback on the transceiver toolkit, to know if the Rx cdr is working or not.
Quartus version 24.2 does not support transceiver IP design example, so I am currently not able to isolate if the problem is tool based or device based.

Best Regards,

paa · Answer

I am attaching a project where I have changed Rx to be mapped to bank 4B and Tx on Bank 4C and signal tap capture.

ar_a_intel · Answer

Hi

It looks like you're encountering a clocking issue with the DisplayPort IP on Agilex 5 where the Transceiver Tx PLL fails to lock, particularly affecting your near-side loopback testing.

To proceed, consider these steps:

Review PLL Configuration: Verify that the Tx PLL settings match the clock requirements of your DisplayPort application, as minor mismatches can lead to locking issues.

Check PMA Direct Clocking: Ensure PMA direct clocking is configured properly in Quartus, as mismatches here could impact Tx lock performance, especially on banks 4B and 4C.

Clock Signals and Layout: Double-check if the clock signal integrity and layout of your design match the specifications for both Rx and Tx paths, as these can impact PLL locking stability, especially at the high data rates used for DisplayPort.

paa · Answer

Hi, Many thanks for your inputs.In your comments, you have mentioned "Verify that the Tx PLL settings match".However, the DP PHY as generated from the example design for Agilex5 does not show any option for the Tx PLL configuration. Havinf said that, I have managed to get the Tx pll locked after tweaking a few parts of the code in NIOS. However, the DP links  are still not connecting to a Monitor (source) or a PC (sink). For ease of debugging I have now reduced the Link speed from 8.1Gbps to 5.4Gbps. With the use of debug registers (mr_rate_detect.v ) I now see that the 23 bit DP clock speed monitor register is set to a value of 1562500 which does not seem to be the standard DP clock frequency.I have set my PMA ref clock to 150MHz (Tx and Rx) for both Bank 4B and Bank 4C. For the sake of experimenting, to see if the clock configuration was working,  I have tried changing the PMA ref clock to 144MHz and saw the clock speed chanigning accordingly ( to 1500000). Please see below the GST Display Port Phy paramters available to me. I do not see any valid address range to access the GTS PHY reconfiguration registers. There seems to be hidden management port interface that seems to be magically connnected to DisplayPort IP Would you recommend that I replace the DisplayPort Phy with the normal GTS PHY ?Best Regards,

ar_a_intel · Answer

Hi

Thanks for your update. Here are some suggestions that may be best for next steps:

· The 1562500 reading may indicate a clocking mismatch. Since you saw changes by adjusting the PMA ref clock, it suggests that the clock path is responsive but may still not match DisplayPort requirements. Confirm the frequency aligns with DisplayPort's expected 1.62, 2.7, 5.4, or 8.1 Gbps configurations.

· Switching to a standard GTS PHY may offer more flexibility for low-level debugging and clock alignment, but it could add complexity if specific DisplayPort optimizations are needed. If the reconfiguration limitations persist, testing with the GTS PHY might help isolate the issue.

paa · Answer

Hi,Thanks for the suggestion. I have been updated that DP Rx features required for our project will be supported in future release(s). Thus, we can close this topic. BR,

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Agilex 5 Transceiver Tx failing for pll lock

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