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PAA
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2 years ago

Agilex 5 Transceiver Tx failing for pll lock

Hi, I am trying to use the Dispaly port IP design example on Agilex 5 device A5ED065BB32AE4SR0 on Arrow AXE5 Eagle development board. However it appears that the Transceiver Tx PLL Lock fails to ...
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PAA
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2 years ago

I am attaching a project where I have changed Rx to be mapped to bank 4B and Tx on Bank 4C and signal tap capture.