Agilex 5 Sulfur Partial Write Issue on F2H ACE‑Lite I/F (256‑bit) with AXI Master of 128‑bit

Hello Intel Support Team,

I am working on an Agilex 5 Sulfur Development Board and implementing an HPS‑based design where a USB Host module (custom logic) acts as an AXI Master and performs memory accesses to SDRAM through the F2H ACE‑Lite interface.

I am seeing an issue related to partial writes when the AXI data width is translated from 128‑bit to 256‑bit before reaching the F2H bridge.

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Design Summary

AXI Master (USB host logic)

• Address width: 32 bits
• Write data width: 128 bits
• Write strobe (WSTRB): 16 bits

Interconnect Path (Platform Designer)

The Master AXI interface passes through the following autogenerated components:

1. mm_interconnect_0_ace5lite_cache_coherency_translator
2. ace5lite_cache_coherency_translator

ACE‑Lite Interface to F2H

• Address width: 32 bits
• Write data width: 256 bits
• Write strobe: 32 bits

Observed Behavior (via SignalTap)

1. The 128‑bit write data is properly expanded to 256‑bit by the translator.
2. The 16‑bit WSTRB is correctly translated to 32‑bit, with only the lower or upper half asserted as expected.
3. The AXI address falls correctly within the SDRAM region.
4. The writes propagate through CCU → MPFE correctly (based on external visibility).

Problem

When reading back SDRAM from software running on the HPS, we observe that:

👉 The entire 256‑bit word in SDRAM is modified,
even though
👉 only 128 bits of WSTRB were asserted on the ACE‑Lite interface.

SignalTap shows the correct WSTRB on the F2H side, but SDRAM readback indicates that the "inactive" 128‑bit lanes are also being overwritten.

Because the HPS subsystem is a hard macro, we cannot probe signals inside the CCU / MPFE / F2H bridge to see what is actually happening after the ACE‑Lite boundary.

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Questions for Intel

We would greatly appreciate guidance on the following:

1. ACE‑Lite 256‑bit Partial Write Support

Are there any documented limitations or required settings for partial‑word writes on the 256‑bit F2H ACE‑Lite interface in Agilex 5?

2. MPFE / SDRAM Controller Behavior

Does the MPFE / CCU / SDRAM controller internally convert all writes to full‑width beats, regardless of WSTRB?
If so, is there a way to ensure correct byte‑enable behavior?

3. Required Qsys Settings?

Are there specific configuration requirements for:

• The ACE‑Lite translator
• Interconnect pipeline stages
• Burst alignment
• Address alignment for partial writes
• Write‑data interleaving settings

4. Debugging Recommendations

Since internal HPS signals cannot be probed, is there:

• Any documented method to trace ACE‑Lite transactions inside HPS?
• Any diagnostic registers or trace capabilities in CCU/MPFE?
• Any recommended debug flow for this type of issue?