Agilex 5: LPDDR5 T-line routing for 1CH x 32 configuration

My question is regarding the requirement for T-line routing when connecting a LPDDR5 memory IC to an Agilex-5 FPGA, using the 1CHx2 configuration.

We are using A5EC043AB32AE2V with a single instance of the LPDDR5 memory controller. The memory component is a single IC, Micron MT62F1G32D2DS-023 WT:B. This is a 32 Gbit component  which has dual die (A and B die) inside. Also, we are using a single memory controller with this chip, not dual controllers.

The Altera recommendation for routing this chip as 1 channel x 32 is Figure 32 in this document: "External Memory Interfaces (EMIF) IP User Guide Agilex™ 5 FPGAs and SoCs" which is document #817467.  Figure 34 also describes the same configuration.

The question I have is about the T-line routing required for the WCK, CK, and CA bus. The T-Line routing is proving to be very difficult to implement in layout and I am wondering if a daisy chain routing style is possible for these signals. If the interface is operated at the max data rate of 3733 Mb/s, the WCK clock will be 1866 MHz and the Signal Integrity engineer is concerned about reflections and signal degradation due to the T-line topology.

Questions:

1. Do you have any reference designs which use the T-line routing style like Figure 32 that I could use as a guide?
2. Is there any subject matter experts at the factory who might have some advice on this routing topology?
3. Is it possible to use a daisy-chain routing style for the WCK, CK, and CA traces, instead of t-line?

Thanks.

Glen