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sbj
New Contributor
New ContributorAgilex 5 GTS Reference Clock Buffer Protection
While reviewing the Agilex 5 GTS documentation, I found that the Input Reference Clock Buffer Protection mechanism automatically disables the reference clock buffer when the input clock is not toggling, and that the documented recovery methods are either reconfiguration or a buffer turn-on request.
For an Agilex 5 design, I would like to clarify:
- Is there any supported method to keep the GTS reference clock buffer permanently enabled?
- Can the Input Reference Clock Buffer Protection mechanism be disabled?
- Is there any alternative to repeatedly issuing a Buffer Turn-on Request when the reference clock may stop and restart during normal operation?
- If not supported, is the documented re-enable procedure the only recommended approach?
1 Reply
BoonBengT_AlteraModerator
Hi sbj
Please find the below response on the question you have:
- The protection mechanism cannot be disabled or permanently overridden, and it automatically turns off the GTS input reference clock buffer when clock activity is absent or outside the 25–380 MHz detection range (Input Reference Clock Buffer Protection).
- The best way to avoid buffer shutoff is to keep the reference clock continuously present and toggling within the supported frequency range (Aging Issue on Unconnected/Used GTS Input Reference Clock Pins).
- If the clock stops, recovery requires either device reconfiguration or a buffer re-enable request through the register method or optional status/control ports (Input Reference Clock Buffer Protection).
- From Quartus Prime 24.3.1 onward, the device provides automatic aging protection, but user logic must still manually re-enable the buffer after the reference clock is restored (Aging Issue on Unconnected/Used GTS Input Reference Clock Pins).
- The recommended recovery sequence is to hold TX and RX PMA reset while the clock is absent, restore the clock, release the resets, request buffer turn-on, and verify the acknowledge and cleared failure status (GTS TX PLL Lock Status Guidelines).
- Enabling reference clock buffer recovery logic in the applicable GTS PHY or Ethernet IP exposes status and control ports that allow user logic to automate the recovery sequence (Low Latency 40G Ethernet IP Parameters).
Best Wishes
BB
