Forum Discussion
Hi
Thanks for sharing your changes.
Unfortunately once stuck, the only method is to power cycle or do a reset.
I have took a look at your project and it is okay. The F2H bridge is disabled.
It is weird that the workaround is not working for you.
Give me sometime while I discuss this with our team.
Could you also share the new logs with F2H disabled? Which point does the boot stuck?
Regards
Jingyang, Teh
Thank you, Jingyang.
Behaviour is same. After I removed using of bridges, I can boot linux even if FPGA is not programmed (or programmed more times). If I programm FPGA core more times, CPU very probably stucks when my application in linux (or devmem) tries to access HPS2FPGA bridge. I had about two situations when everything went OK after 5 tries of reprogramming in u-boot.
Hopefully I will be able to test the design on other AXE5-Eagle kit (we need two kits to work in parallel) and in the next two weeks it will be available.
We are now doing some experiments with Quartus 25.1, but it seems that more things must be changed. We can compile design OK, but if we use Q25.1 to generate (jic/rpd) files then we are not able to programm core.rbf even from u-boot and linux boot stucks with some errors. If we use Q24.3.1 for generating files compiled by Q25.1 it seems to work ok. So we will wait with migration, since Arrow provide GHRD, u-boot and linux examples compatible with Q25.1.
Regards,
Martin