Forum Discussion
Occasional ContributorAgilex 3 PLL in Source Synchronous mode ?
Occasional ContributorHi Aqid,
Yes, I confirm again that the Atum A3 nano is the Terasic board we're trying to use.
Terasic didn't want to share the complete schematics, even if we are a distributor, but we got some pages and the details about the PHY details including the bootstrap settings (RX[2:0]=100, TX[2:0]=100).
The pinout is what we used and it fails. Having access to the PHY MDIO doesn't help..
The PHY is using HVIOs : not smart...
As I explained, we found no way to close the RGMII timings on the Intel Agilex 5 kit other than using the PLL in Source Synchronous mode.
Hence the conclusion that the Atum A3 nano FPGA Eth PHY cannot be used (reliably or at all). It's a board design mistake (anyway, IMO, choosing RGMII is a poor choice since Cyclone V).
The only FPGA feature that could be demonstrated on the Atum A3 board seems to be the MIPI link (tbv).
Regular ContributorYes, I agree that for this board, the validated RGMII Gigabit Ethernet through a source-synchronous IOPLL is not available with the current pinout. Remaining options on this kit are limited to whatever Terasic documents for their Ethernet example (if they provide that), or other interfaces that are actually brought out, such as MIPI as you noted.
