Agilex 3 A3CZ100BM16AE7S – 3.3 V HVIO input always reads HIGH

Hi,

I am bringing up a new board using an Agilex 3 A3CZ100BM16AE7S and I am seeing a strange issue with the HVIO input path.

I am using Quartus Prime Pro 25.3.1.

The FPGA configures successfully through JTAG, FPGA logic is running, HVIO outputs work correctly, and inputs on non-HVIO banks also work correctly. However, the 3.3 V HVIO inputs always appear to be read as logic HIGH.

My current simple test uses:

Device: A3CZ100BM16AE7S
Quartus Prime Pro: 25.3.1
TP1: AF27
HVIO Bank: 5B
Direction: Input
I/O standard: 3.3-V LVCMOS
VCCIO_HVIO = 3.3 V
VCCPT_HVIO = 1.8 V
VCC/VCCP = 0.75 V

The FPGA power rails have been checked and appear correct.

A very simple test was first used:
TP1 is 3.3V HVIO pin and TP13 is non-HVIO pin
TP13 <= TP1;
When TP1 is physically LOW, TP13 still indicates that TP1 is HIGH.

I also tested:
TP13 <= not TP1;
With TP1 physically at 0 V, TP13 becomes LOW, which again indicates that the FPGA internally sees TP1 as logic 1.

I also tested the programmable weak pull-up/down on AF27 (HVIO pin).
With weak pull-up enabled:
TP1 ≈ 3.3 V (with the multi-meter)
With weak pull-down enabled:
TP1 ≈ 0 V (with the multi-meter)

The weak pull-up/down therefore physically changes the voltage at the FPGA pin correctly.

I then enabled the internal weak pull-up and added an external 1 kΩ resistor from TP1 to GND.

The measured TP1 voltage becomes approximately:
TP1 ≈ 150 mV
which is consistent with the internal ~20 kΩ pull-up and external 1 kΩ pull-down.

However, the FPGA still reads the input as HIGH.

Has anyone seen a similar issue with Agilex 3 HVIO input buffers, particularly with the A3CZ100BM16A device ?
Is there any additional HVIO input configuration, device setting, programming option, or known Quartus issue that I may be missing?
As far as I understand, a standard 3.3-V LVCMOS input on an HVIO bank should work directly without requiring any special input-enable configuration.
Any suggestions for further tests would be greatly appreciated.

Thanks.

Paul