Agilex 3 A3CZ100BM16AE7S – 3.3 V HVIO input always reads HIGH

Hi Paul,

This is a well-documented hardware issue specific to Agilex 3 devices that include GTS transceivers. Your symptom matches it exactly. The issue affects the HVIO bank adjacent to the GTS transceiver bank and is related to specific power and pin connection conditions during board design. Refer here: Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration?

Your A3CZ100BM16AE7S has 4 transceivers (XCVR: 4) https://docs.altera.com/v/u/docs/833123/agilextm-3-fpgas-and-socs-c-series-product-table , so the GTS transceiver bank is present and powered on your board. Bank 5B is the HVIO bank adjacent to the GTS transceiver bank, which is exactly the bank you're using (AF27, HVIO Bank 5B).

The most likely root cause is the RCOMP pin for the GTS transceiver bank being left unconnected on your board. Check that pin first.

Hope that gets you unblocked quickly!