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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex™ 7 FPGA I-Series Development Kit - Only one PCIe RP Gen4x4 on the R-Tile

Hello,

I would like to use only one Root Port PCIe Gen4x4 on the R-Tile of an Agilex 7 I-Series.

When I create the PCIe IP, four PCIe IP of Gen4x4 are created.

What should be done to disable the three others PCIe IP Gen4x4 ?

Or, how to tell the IP wizard to generate only PCIe IP ?

Thanks for help.

Serge

Other Ips

5 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi Serge93,


    Thanks for reaching out.


    If you choose Gen4 4x4 mode, the system will generate a PCIe IP with four x4's PCIe link through PCIe port bifurcation. According to the Table 13., 4x4 bifurcation mode will have Port 0, Port 1, Port 2, and Port 3 active.

    https://www.intel.com/content/www/us/en/docs/programmable/683501/24-3-1/pcie-port-bifurcation-and-phy-channel.html


    If you wish to use only one Gen4 1x4, you can connect only the signals for Port 0, and leave the other ports' signal floating. For example, leave rx_n_in4 to rx_n_in15 and rx_p_in4 to rx_p_in15 unconnected, and do the same for tx signals. Additionally, leave other signals that starts with p1_x, p2_x, and p3_x, which are dedicated to the respective ports unconnected.


    Thanks.

    Best Regards,

    Ven


    • Serge93's avatar
      Serge93
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      HelloVen,

      Thank you for your answer.

      But I am a little bit confusing about your example on selecting Port 0.

      From the table below, in 4x4 mode, Port 0 is connected to Pcie lanes 4-7

      So the lanes to leave floating are Pcie lanes 8-11, 0-3 and 12-15, correct ?

      Thanks.

      Serge

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi Serge,


    Yes, you are absolutely right. My apologies for the oversight on the table.

    Port 0 (x4) uses lanes 4-7. Therefore, it is to leave PCIe lanes 8-11, 0-3, and 12-15 floating.


    Thanks.

    Best Regards,

    Ven


    • Serge93's avatar
      Serge93
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Thank you very much Ven.

      Have a nice day.
      Serge

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi Serge,


    Thanks, you have a great day as well!


    I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


    Best Regards,

    Ven