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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex™ 7 FPGA I-Series Development Kit - Only one PCIe RP Gen4x4 on the R-Tile

Hello, I would like to use only one Root Port PCIe Gen4x4 on the R-Tile of an Agilex 7 I-Series. When I create the PCIe IP, four PCIe IP of Gen4x4 are created. What should be done to disable the t...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Serge,


Yes, you are absolutely right. My apologies for the oversight on the table.

Port 0 (x4) uses lanes 4-7. Therefore, it is to leave PCIe lanes 8-11, 0-3, and 12-15 floating.


Thanks.

Best Regards,

Ven


  • Serge93's avatar
    Serge93
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Thank you very much Ven.

    Have a nice day.
    Serge